The present invention relates to a method for polishing a silicon wafer to provide an extremely flat, damage-free mirror surface, which is especially suitable for semiconductor devices. The present invention also relates to a method for producing a silicon wafer.
Conventionally, in order to provide a mirror surface and the flatness required for semiconductor device fabrication, polishing is accomplished by a mechanochemical process in which a polishing pad of synthetic fibers, an alkaline polishing fluid, and fine silica particles are used. The silicon wafer is supported between a base plate covered with a polishing pad and a carrier plate to which the wafer adheres, or the wafer may be held between two base plates covered with polishing pads about 2 mm thick. A pressure of 100 to 500 g/cm.sup.2 is applied to the wafer surface. The wafer is mechanochemically polished by means of relative movement between the base plate and the wafer, as for example, by the rotation of the base plate and the carrier plate, supplying polishing fluid which includes an alkaline fluid in a pH range of 10 to 12, and using polishing particles of high-purity silica of 0.02 to 0.10 .mu.m.
With such a method, the pressure is applied to the surface of the wafer via the cloth, whereby a uniform pressure is generated over the entire surface owing to the compressive deformation of cloth, and therefore the differences in rate of among areas of the silicon wafer are small.
However, a problem develops because of the generally uniform rate of removal as shown in FIG. 1. In FIG. 1, a silicon wafer 20 includes a surface 22 to be polished which has a variation in thickness. In the polishing process, a volume 24 of the silicon wafer is removed and a surface 26 is exposed. According to the generally uniform rate of removal, thickness variations still remain on the surface 26. In order to finish the surface 26 to the flatness required for VLSI fabrication, much time is spent removing a relatively large amount of material. Recently, to meet the stricter thickness variation specifications, harder and harder polishing cloths (pads) are employed, however reducing the total thickness variation to less than 2 .mu.m is nonetheless very difficult.
Recently, in device development design, smaller size and higher integration are increasingly important considerations. To meet these requirements, we must consider the use of a step-and-repeat-camera in the photolithographic process, as well as for example, focusing, condition of the surface with which focusing must coincide during resist coating, film formation, and etching off. Practically, for example, to produce a submicron device, thickness variations of wafers at 15.times.15 mm or 20.times.20 mm must be less than 1 .mu.m, preferably 0.5 .mu.m. The requirement for total thickness variation of a wafer used must now therefore be less than 2 .mu.m.
In recent years, the dielectric-isolation structure, the Bi-CMOS structure, and the SOI (Silicon-On-Insulator) structure devices were developed. In the SOI structure, and island of monocrystaline silicon, polycrystaline silicon, or amorphous silicon is formed; and a dielectric or insulator area is also formed on a substrate. It is necessary to polish the silicon island and the dielectric area to be damage-free according to the method described above. In addition, the thickness of the silicon island must be adjusted to the device to be fabricated. The circuit defined by the silicon island must have a desirable properties.
In the method, for example, a substrate 30 made of a monocrystaline silicon or polycrystaline silicon is first prepared as shown in FIG. 2. An insulator raised pattern 32 of SiO.sub.2 is formed on one surface of the substrate 30. Next, by means of a thin-film forming method such as CVD (Chemical Vapor Deposition), a silicon layer 34 made of monocrystaline or polycrystaline silicon is formed on the surface of the substrate 30 in such a manner that the insulator pattern 32 is surrounded by the substrate 30 and the silicon layer 34, so that the unfinished silicon wafer shown in FIG. 2 is produced with some thickness variations.
To flatten the surface of the wafer, three methods are known, (a) the etch-back method, (b) the reflow method, and (c) the selective polishing method. However, the etched back method requires much processing and only produces a tolerance of .+-.0.2 .mu.m, and the reflow method is applied only to the wiring process. Therefore, the selective polishing process is the only solution.
After initial processing, the selective polishing method is applied to finish the outer surface of the silicon layer 34, so that the silicon layer is surrounded laterally by the insulator pattern as shown in FIG. 3. In the polishing method, when the polishing removal reaches the insulator pattern 32, the removal rate becomes very low. Then, the polishing pad is deformed compressively to excavate the silicon island 40 as shown in FIG. 3. (In FIG. 3, numbers 36 and 38 designate the surfaces of the silicon wafer before and after polishing, respectively.) Therefore, the thicknesses of the crystal island on which circuit is later to be fabricated varies, differing from an identical finished wafer shown in FIG. 4, and thus defocusing is occurred in the photolithographic process.
If it is necessary that the device structure has a certain thickness remaining over the insulator pattern 32 as shown in FIG. 5. Polishing with the polishing pad must not flatten the surface 38 nor control the thickness of the remained silicon layer 34 over the insulator pattern 32.